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| CMOS ST-BUSTM Family MT8985 Enhanced Digital Switch Data Sheet Features * * * * * * * * * 256 x 256 channel non-blocking switch Programmable frame integrity for wideband channels Automatic identification of ST-BUS/GCI interface backplanes Per channel tristate control Patented message mode Non-multiplexed microprocessor interface Single +5 volt supply Available in DIP-40, PLCC-44 and QFP-44 packages Pin compatible with MT8980 device Ordering Information September 2005 MT8985AE 40 Pin PDIP Tubes MT8985AP 44 Pin PLCC Tubes MT8985AL 44 Pin MQFP Trays MT8985APR 44 Pin PLCC Tape & Reel MT8985AP1 44 Pin PLCC* Tubes MT8985APR1 44 Pin PLCC* Tape & Reel MT8985AE1 40 Pin PDIP* Tubes MT8985AL1 44 Pin MQFP* Trays *Pb Free Matte Tin -40C to +85C Switch (DX). It is pin compatible with the MT8980D and retains all of the MT8980D's functionality. This VLSI device is designed for switching PCM-encoded voice or data, under microprocessor control, in digital exchanges, PBXs and any ST-BUS/MVIP environment. It provides simultaneous connections for up to 256 64 kb/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s stream. As the main function in switching applications, the device provides per-channel selection between variable or constant throughput delays. The constant throughput delay feature allows grouped channels such as ISDN H0 to be switched through the device maintaining its sequence integrity. The MT8985 is ideal for medium sized mixed voice/data switch and voice processing applications. Applications * * * * * * Medium size digital switch matrices Hyperchannel switching (e.g., ISDN H0) ST-BUS/MVIPTM interface functions Serial bus control and monitoring Centralized voice processing systems Data multiplexer Description The MT8985 Enhanced Digital Switch device is an upgraded version of the popular MT8980D Digital C4i F0i VDD VSS ODE STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 Serial to Parallel Converter Data Memory Frame Counter Output MUX Parallel to Serial Converter STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 Control Register Connection Memory Control Interface DS CS R/W A5/ A0 DTA D7/ D0 CSTo Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT8985 Changes Summary The following table captures the changes from the May 2005 issue. Page 7 Item Figure 3 - "Address Memory Map" NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC Data Sheet Change * corrected Address Memory Map NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 DTA STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 A3 A4 A5 DS R/W 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 CSTo ODE STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4 D5 D6 D7 CS 40 PIN PLASTIC DIP STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2 NC A3 A4 A5 DS R/W CS D7 D6 D5 NC 44 PIN PLCC Figure 2 - Pin Connections 2 Zarlink Semiconductor Inc. NC A3 A4 A5 DS R/W CS D7 D6 D5 NC 44 PIN QFP 12 13 14 15 16 17 18 19 20 21 22 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 MT8985 Pin Description Pin # 40 DIP 44 44 PLCC QFP Data Sheet Name Description 1 2-9 10 11 2 40 DTA Data Acknowledgement (Open Drain Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. 3-5 41-43 STi0- ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32 7-11 1-5 STi7 channels at data rates of 2.048 Mbit/s. 12 13 6 7 VDD F0i +5 Volt Power Supply rail. Frame Pulse (Input): This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS and GCI. Clock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams. 12 14 8 C4i 13-18 15-17 9-11 A0-A5 Address 0 to 5 (Inputs). These lines provide the address to MT8985 internal 19-21 13-15 registers. 19 22 16 DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. Read/Write (Input). This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Chip Select (Input). Active low input enabling a microprocessor read or write of control register or internal memories. 20 21 23 24 17 18 R/W CS 22-29 25-27 19-21 D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data 29-33 23-27 in the internal control register, connect memory high, connect memory low and data memory. 30 34 28 VSS Ground Rail. 31-38 35-39 29-33 STo7- ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These 41-43 35-37 STo0 streams are composed of 32 channels at data rates of 2.048 Mbit/s. 39 44 38 ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial outputs. If this input is low STo0-7 are high impedance. If this input is high each channel may still be put into high impedance by software control. CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations. NC No Connection. 40 1 39 6, 18, 12,22 34, 28, 44 40 3 Zarlink Semiconductor Inc. MT8985 Functional Description Data Sheet With the integration of voice, video and data services into the same network, there has been an increasing demand for systems which ensure that data at N x 64 Kbit/s rates maintain frame sequence integrity while being transported through time slot interchange circuits. Existing requirements demand time slot interchange devices performing switching with constant throughput delay while guaranteeing minimum delay for voice channels. The MT8985 device provides both functions and allows existing systems based on the MT8980D to be easily upgraded to maintain the data integrity while multiple channel data are transported. The device is designed to switch 64 kbit/s PCM or N x 64 kbit/s data. The MT8985 can provide both frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis. By using Zarlink Message mode capability, the microprocessor can access input and output time slots on a per channel basis to control devices such as the Zarlink MT8972, ISDN Transceivers and T1/CEPT trunk interfaces through the ST-BUS interface. Different digital backplanes can be accepted by the MT8985 device without user's intervention. The MT8985 device provides an internal circuit that automatically identifies the polarity and format of frame synchronization input signals compatible to ST-BUS and GCI interfaces. Device Operation A functional block diagram of the MT8985 device is shown in Figure 1. The serial ST-BUS streams operate continuously at 2.048 Mb/s and are arranged in 125 s wide frames each containing 32 8-bit channels. Eight input (STi0-7) and eight output (STo0-7) serial streams are provided in the MT8985 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as required in ST-BUS and GCI specifications. Data Memory The received serial data is converted to parallel format by the on-chip serial to parallel converters and stored sequentially in a 256-position Data Memory. The sequential addressing of the Data Memory is generated by an internal counter that is reset by the input 8 kHz frame pulse (F0i) marking the frame boundaries of the incoming serial data streams. Depending on the type of information to be switched, the MT8985 device can be programmed to perform time slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, the variable delay mode can be selected ensuring minimum throughput delay between input and output data. In multiple or grouped channel data applications, the constant delay mode can be selected maintaining the integrity of the information through the switch. Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input (connection mode) or it can be originated from the microprocessor (message mode). If a channel is configured in connection mode, the source of the output data is the Data Memory. If a channel is configured in message mode, the source of the output data is the Connect Memory Low. Data destined for a particular channel on the serial output stream is read from the Data or Connect Memory Low during the previous channel time slot. This allows enough time for memory access and internal parallel to serial conversion. Connection and Message Modes In connection mode, the addresses of input source for all output channels are stored in the Connect memory Low. The Connect Memory Low locations are mapped to each location corresponding to an output 64 kb/s channel. The contents of the Data memory at the selected address are then transferred to the parallel to serial converters. By having the output channel to specify the input channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcasting facility in the switch. 4 Zarlink Semiconductor Inc. MT8985 Data Sheet In message mode the CPU writes data to the Connect Memory Low locations which correspond to the output link and channel number. The contents of the Connect Memory Low are transferred to the parallel to serial converter one channel before it is to be output. The Connect Memory Low data is transmitted each frame to the output until it is changed by the CPU. The per-channel functions available in the MT8985 are controlled by the Connect Memory High bits, which determine whether individual output channels are selected into specific conditions such as: message or connection mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. In addition, the Connect Memory High provides one bit to allow the user to control the state of the CSTo output pin. If an output channel is set to three-state condition, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel three-state control, all channels on the TDM outputs can be placed in high impedance at one time by pulling the ODE input pin in LOW. This overrides the individual perchannel programming on the Connect Memory High bits. The Connect Memory data is received via the Microprocessor Interface at D0-D7 lines. The addressing of the MT8985 internal registers, Data and Connect memories is performed through address input pins and some bits of the device's Control register. The higher order address bits come from the Control register, which may be written or read through the microprocessor interface. The lower order address bits come directly from the external address line inputs. For details on the device addressing, see Software Control and Control register description. Serial Interface Timing The MT8985 master clock (C4i) is a 4.096 MHz allowing serial data link configuration at 2.048 Mb/s to be implemented. The MT8985 frame synchronization pulse can be formatted according to ST-BUS or GCI interface specifications; i.e., the frame pulse can be active in HIGH (GCI) or LOW (ST-BUS). The MT8985 device automatically detects the presence of an input frame pulse and identifies the type of backplane present on the serial interface. Upon determining the correct interface connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. In ST-BUS mode, every second falling edge of the 4.096 MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. In GCI mode, every second rising edge of the 4.096 MHz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries. Delay through the MT8985 The transfer of information from the input serial streams to the output serial streams results in a delay through the MT8985 device. The delay through the MT8985 device varies according to the mode selected in the V/C bit of the connect memory high. Variable Delay Mode The delay in this mode is dependent only on the combination of source and destination channels and it is not dependent on the input and output streams. The minimum delay achievable in the MT8985 device is 3 time slots. In the MT8985 device, the information that is to be output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if the input channel has to be output in the two channels succeeding (n+1 and n+2) the channel position as the information is input. The information switched to the third timeslot after the input has entered the device (for instance, input channel 0 to output channel 3 or input channel 30 to output channel 1), is always output three channels later. Any switching configuration that provides three or more timeslots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. Table 1 shows the possible delays for the MT8985 device in Variable Delay mode: 5 Zarlink Semiconductor Inc. MT8985 Input Channel n n Output Channel m=n, n+1 or n+2 m>n+2 Throughput Delay m-n + 32 timeslots m-n time slots Data Sheet n m Microprocessor Port The MT8985 microprocessor port has pin compatibility with Zarlink MT8980 Digital Switch device providing a nonmultiplexed bus architecture. The parallel port consists of an 8 bit parallel data bus (D0-D7), six address input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control registers, Connection Memory High, Connection Memory Low and the Data Memory. All locations are read/written except for the data memory which can be read only. Accesses from the microport to the connection memory and the data memory are multiplexed with accesses from the input and output TDM ports. This can cause variable Data Acknowledge delays (DTA). In the MT8985 device, the DTA output provides a maximum acknowledgement delay of 800 ns for read/write operations in the Connection Memory. However, for operations in the Data Memory (Message Mode), the maximum acknowledgement delay can be 1220 ns. 6 Zarlink Semiconductor Inc. MT8985 A5 0 1 1 1 1 1 1 1 1 A4 0 0 0 * * * * * 1 A3 0 0 0 * * * * * 1 A2 0 0 0 * * * * * 1 A1 0 0 0 * * * * * 1 A0 0 0 1 * * * * * 1 LOCATION Control Register Channel 0 Channel 1 * * * * * Channel 31 Data Sheet Figure 3 - Address Memory Map Note: "x" Don't care Software Control The address lines on the microprocessor interface give access to the MT8985 internal registers and memories. If the A5,A1,A0 address line inputs are LOW, then the MT8985 Internal Control Register is addressed (see Figure 3). If A5 input line is HIGH, then the remaining address input lines are used to select Memory subsections of 32 locations corresponding to the number of channels per input or output stream. As explained in the Control register description, the address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of the MT8985 Data and Connect memories. The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream Address bits (see Figure 4). The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory to be chosen, and the Stream Address bits define an internal memory subsections corresponding to input or output ST-BUS streams. Bit 7 (Split Memory) of the Control register allows split memory operation whereby reads are from the Data memory and writes are to the Connect Memory LOW. The Message Enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the contents of the Connect Memory LOW (CML) are output on the ST-BUS output streams once every frame unless the ODE input pin is LOW. If ME bit is HIGH, then the MT8985 behaves as if bits 2 (Message Channel) and 0 (Output Enable) of every Connect Memory HIGH (CMH) locations were set to HIGH, regardless of the actual value. If ME bit is LOW, then bit 2 and 0 of each Connect Memory HIGH location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated ST-BUS output channel is in Message mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an output. If the ODE input pin is LOW, then all serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH) or disables (if LOW) the output drivers for the corresponding individual STBUS output stream and channel. The contents of bit 1 (CSTo) of each Connection Memory High location (see Figure 5) is output on CSTo pin once every frame. The CSTo pin is a 2048 Mbit/s output which carries 256 bits. If CSTo bit is set HIGH, the corresponding bit on CSTo output is transmitted in HIGH. If CSTo bit is LOW, the corresponding bit on the CSTo output is transmitted in LOW. The contents of the 256 CSTo bits of the CMH are transmitted sequentially on to the CSTo output pin and are synchronous to the ST-BUS streams. To allow for delay in any external control circuitry the contents of the CSTo bit is output one channel before the corresponding channel on the ST-BUS streams. For example, the contents of CSTo bit in position 0 (ST0, CH0) of the CMH, is transmitted synchronously with ST-BUS channel 31, bit 7. The contents of CSTo bit in position 32 (ST1, CH0) of the CMH is transmitted during ST-BUS channel 31 bit 6. Bit V/C (Variable/Constant Delay) on the Connect Memory High locations allow per-channel selection between Variable and Constant throughput delay capabilities. 7 Zarlink Semiconductor Inc. MT8985 Data Sheet 7 SM 6 ME 5 X 4 MS1 3 MS0 2 STA2 1 STA1 0 STA0 BIT 7 NAME SM DESCRIPTION Split Memory. When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. The Memory Select bits need to be set to specify the memory for the operations. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. Message Enable. When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when in High Impedance. When 0, the Connection Memory bits for each channel determine what is output. Memory Select Bits. The memory select bits operate as follows: 0-0 - Not to be used 0-1 - Data Memory (read only from the CPU) 1-0 - Connection Memory Low 1-1 - Connection Memory High Stream Address Bits 2-0. The number expressed in binary notation on these bits refers to the input or output ST-BUS stream which corresponds to the subsection of memory made accessible for subsequent operations. Figure 4 - Control Register Bits 6 ME 4-3 MS1-MS0 2-0 STA2-0 x = Don't care Initialization of the MT8985 On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple MT8985 ST-BUS outputs are tied together to form matrices, as these outputs may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition. 8 Zarlink Semiconductor Inc. MT8985 Data Sheet 7 X 6 V/C 5 X 4 X 3 X 2 MC 1 CSTo 0 OE BIT 6 2 NAME V/C MC DESCRIPTION Variable/Constant Throughput Delay Mode. This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes on a per-channel basis. Message Channel. When 1, the contents of the corresponding location in Connection Memory Low are output on the corresponding channel and stream. When 0, the contents of the programmed location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location's channel and stream. CSTo Bit. This bit drives a bit time on the CSTo output pin. Output Enable. This bit enables the output drivers on a per-channel basis. This allows individual channels on individual streams to be made high-impedance, allowing switch matrices to be constructed. A HIGH enables the driver and a LOW disables it. Figure 5 - Connection Memory High Bits 1 0 CSTo OE x = Don't care 7 SAB2 6 SAB1 5 SAB0 4 CAB4 3 CAB3 2 CAB2 1 CAB1 0 CAB0 BIT 7-5 4-0* NAME SAB2-0* CAB4-0* DESCRIPTION Source Stream Address bits. These three bits are used to select eight source streams for the connection. Bit 7 of each word is the most significant bit. Source Channel Address bits 0-4. These five bits are used to select 32 different source channels for the connection (The ST-BUS stream where the channel is present is defined by bits SAB2-0). Bit 4 is the most significant bit. * If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. Figure 6 - Connection Memory Low Bits During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two connected ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the CMHb0s. 9 Zarlink Semiconductor Inc. MT8985 Applications Typical Exchange, PBX or Multiplexer Data Sheet Figure 7 shows a typical implementation of line cards being interconnected through a central routing matrix that can scale up in channel capacity to accommodate different number of ports depending on the application. In a configuration where the switched services utilize concatenated or grouped time slots to carry voice, data and video (channels of 128, 256 Kb/s, ISDN H0 and others), the central routing matrix has to guarantee constant throughput delay to maintain the sequence integrity between input and output channels. Figure 7 shows an example where the MT8985 device guarantees data integrity when data flows from the T1/E1 to the S/U interface links and viceversa. Modern technologies available today such as Frame Relay network using dedicated fractional T1 are one of the key applications for the MT8985 device. To other lines Basic Rate Line Card Layers 2&3 Entity ST-BUS ST-BUS To other lines MT8930/31 S/U MT8910 MT8972 C P U ROUTING MATRIX MT8985's ST-BUS T1/E1 Link MT8940/ MT8941 MH89760/ MH89790 MT8920 C Primary Rate Card Figure 7 - Typical Exchange, PBX or Multiplexer Configuration 10 Zarlink Semiconductor Inc. MT8985 ISDN Desktops (2B+D) ****** Analog Connections ****** Server 2 Server 1 Data Sheet T1 T1 ****** Server 4 Isochronous Network E1 Access to Public Network Server 3 T1/E1 n x 64 Connections (e.g. Video) Figure 8a - Private Isochronous Network Low Latency Isochronous Network In today's local working group environment, there is an increasing demand for solutions on interconnection of desktop and telephone systems so that mixed voice, data and video services can be grouped together in a reliable network allowing the deployment of multimedia services. Existing multimedia applications require a network with predictable data transfer delays that can be implemented at a reasonable cost. The Low Latency Isochronous Network is one of the alternatives that system designers have chosen to accommodate this requirement (see Figure 8a). This network can be implemented using existing TDM transmission media devices such as ISDN Basic (S or U) and Primary rates trunks (T1 and CEPT) to transport mixed voice and data signals in grouped time slots; for example, 2B channels in case of ISDN S or U interfaces or up to 32 channels in case of a CEPT link. Figure 8b shows a more detailed configuration whereby several PCs are connected to form an Isochronous network. Several services can be interconnected within a single PC chassis through the standardized Multi Vendor Integration Protocol (MVIP). Such an interface allows the distribution and interconnection of services like voice mail, integrated voice response, voice recognition, LAN gateways, key systems, fax servers, video cards, etc. The information being exchanged between cards through the MVIP interface on every computer as well as between computers through T1 or CEPT links is, in general, of mixed type where 64Kb/s and N*64Kb/s channels are grouped together. When such a mixed type of data is transferred between cards within one chassis or from one computer to another, the sequence integrity of the concatenated channels has to be maintained. The MT8985 device suits this application and can be used to form a complete non-blocking switch matrix of 512 channels (see Figure 9). This allows 8 pairs of ST-BUS streams to be dedicated to the MVIP side whereas the remaining 8 pairs are used for local ancillary functions in typical dual T1/E1 interface applications (Figure 10). Another application of the MT8985 in an MVIP environment is to build an ISDN S-interface card (Figure 11). In this card, 7 pairs of ST-BUS streams are connected to the MVIP interface while the remaining pair is reserved for the interconnection of Zarlink MT8930 (SNIC), MT8992 (H-PHONE) and the MVIP interface. 11 Zarlink Semiconductor Inc. MT8985 Data Sheet To Video, Data, Fax and other services MVIP BUS Server 1 ST-BUS MH89760B MH89790B MT8930B MT8985s (x4) ISDN S-Interface * * MT8930B * * * * * Local T1/E1 Link MVIP BUS Server 3 Server 3 * * * (256 PORT SWITCH MODULE) MH89760B/790B MH89760B/790B ST-BUS MT8985s (x4) MT8985 MT8985 ST-BUS MH89760B T1 * * * MT8985 MH89760B/790B HDLC MT8985 MH89790B E1 Dual T1/E1 Card Local T1/E1 Link MH89760B MH89790B ST-BUS MT8972B or ANALOG MT8985s (x4) * * * * * Server 2 MVIP BUS To Video, Data, Fax Services Local Environment Public Network Access Figure 8b - Implementation of an Isochronous Network Using Zarlink Components 12 Zarlink Semiconductor Inc. MT8985 Data Sheet 8 Input Streams From MVIP MT8985 #1 CSTo 8 Output Streams to MVIP MVIP Direction 8 Input On-Board ST-BUS Streams MT8985 #2 CSTo 8 Output On-Board ST-BUS Streams MVIP Enable MT8985 #3 MT8985 #4 Figure 9 - 512-Channel Switch Array 13 Zarlink Semiconductor Inc. MT8985 Data Sheet MVIP HEADER MVIP STo0-7 FDL HDLC MT8952B SWITCH MT8985 512 Channel Switch Matrix MVIP STi0-7 SWITCH MT8985 FDL HDLC MT8952B T1/E1 MH89760B or MH89790B HDLC MT8952B DPLL MT8941 ANALOG D-PHONE MT8992/93 PC INTERFACE SWITCH MT8985 SWITCH MT8985 T1/E1 MH89760B or MH89790B HDLC MT8952B Figure 10 - Dual T1/E1 Card Functional Block Diagram 14 Zarlink Semiconductor Inc. MT8985 Data Sheet MVIP HEADER MVIP STo1-7 STi7-1 SWITCH MATRIX STi0 S INTERFACE HDLC MT8930B DPLL MT8941 DTMF RECEIVER MT8870 DIGITAL PHONE HDLC MT8992/93 PC INTERFACE MT8985 STo0 MVIP STi1-7 STo7-1 Figure 11 - S-Access Card Functional Block Diagram 15 Zarlink Semiconductor Inc. MT8985 Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 VDD - VSS Voltage on Digital Inputs Voltage on Digital Outputs Current at Digital Outputs Storage Temperature Package Power Dissipation VI VO IO TS PD -65 Symbol Min. -0.3 VSS-0.3 VSS-0.3 Max. 7 Data Sheet Units V V V mA C W VDD+0.3 VDD+0.3 40 +150 2 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 Operating Temperature Positive Supply Input Voltage Sym. TOP VDD VI Min. -40 4.75 0 Typ. 25 5.0 Max. +85 5.25 VDD Units C V V Test Conditions Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 O U T P U T S I N P U T S Supply Current Input High Voltage Input Low Voltage Input Leakage (input pins) Input Leakage (I/O pins) Input Pin Capacitance Output High Voltage Output High Current Output Low Voltage Output Low Current High Impedance Leakage Output Pin Capacitance Sym. IDD VIH VIL IIL 34 CI VOH IOH VOL IOL IOZ CO 8 5 10 5 2.4 10 15 0.4 8 2.0 0.8 5 100 Min. Typ. 10 Max. 15 Units mA V V mA pF V mA V mA mA pF IOH = 10 mA Sourcing. VOH=2.4V IOL = 5 mA Sinking. VOL = 0.4V VO between VSS and VDD VI between VSS and VDD Test Conditions Outputs unloaded Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. 16 Zarlink Semiconductor Inc. MT8985 S1 is open circuit except when testing output levels or high impedance states. S2 is switched to VDD or V SS when testing output levels or high impedance states. Data Sheet Test Point RL S1 CL VSS S2 VDD Output Pin VSS Figure 12 - Output Test Load AC Electrical Characteristics - ST-BUS Timing - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 Frame Pulse width 2 Frame Pulse setup time 3 Frame Pulse hold time 4 STo delay Active to Active 5 STi setup time 6 STi hold time 7 Clock period 8 CK Input Low 9 CK Input High 10 Clock Rise/Fall Time Sym. tF0iW tF0iS tF0iH tDAA tSTiS tSTiH tC4i tCL tCH tr,tf 20 20 200 85 85 244 122 122 300 150 150 10 10 20 45 Min. Typ. 244 190 190 100 Max. Units ns ns ns ns ns ns ns ns ns ns CL=150 pF Test Conditions Timing is over recommended temperature & power supply voltages (VDD=5V5%, VSS=0V, TA=-40 to 85C). Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. 17 Zarlink Semiconductor Inc. MT8985 Data Sheet tF0iW F0i 2.0V 0.8V tF0iH 2.0V tC4i tCH tCL C4i 0.8V tF0iS tf tr tDAA STo 2.0V 0.8V Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 tSTiH Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 0 Bit 5 tSTiS 2.0V 0.8V STi Ch. 31 Bit 0 Ch. 0 Bit 5 Figure 13 - ST-BUS Timing AC Electrical Characteristics - GCI Timing Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 Clock Period Pulse Width Frame Width High Frame Setup Frame Hold Data Delay/Clock Active to Active Serial Input Setup Serial Input Hold Clock Rise/Fall Time Sym. tC4i tCL, tCH tWFH tF0iS tF0iH tDAA tSTiS tSTiH tr,tf Min. 150 73 Typ. 244 122 244 Max. 300 150 Units ns ns ns Test Conditions 10 20 45 20 20 190 190 100 ns ns ns ns ns CL=150 pF 10 ns Timing is over recommended temperature & power supply voltages (VDD=5V5%, VSS=0V, TA=-40 to 85C). Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. 18 Zarlink Semiconductor Inc. MT8985 Data Sheet C4i F0i STi/ STo bit 0 bit 1 bit 2 bit 3 Note: bit 0 identifies the first bit of the GCI frame See Detail a tr C4i 2.0V 0.8V tf tCL tCH tC4i tWFH F0i 2.0V 0.8V tF0iS tF0iH STo 2.0V 0.8V tDAA STi 2.0V 0.8V tSTiS tSTiH Detail a Figure 14 - GCI Timing AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristics 1 2 3 4 O U T P U T S Sym. tSAZ tSZA tOED tXCD Min. Typ. Max. 100 100 65 Units ns ns ns ns Test Conditions RL=1 K*, CL=150 pF CL=150 pF RL=1 K*, CL=150 pF CL=150 pF STo0/7 Delay - Active to High Z STo0/7 Delay - High Z to Active Output Driver Enable Delay CSTo Output Delay 0 60 Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 19 Zarlink Semiconductor Inc. MT8985 Data Sheet Bit Cell Boundary (GCI) C4i 2.0V 0.8V (ST-BUS) STo0 2.4V to STo7 0.4V tSAZ STo0 2.4V to STo7 0.4V * * tSZA 2.4V CSTo 0.4V tXCD Figure 15 - Serial Outputs and External Control ODE 2.0V 0.8V STo0 2.4V to STo7 0.4V * * tOED tOED Figure 16 - Output Driver Enable 20 Zarlink Semiconductor Inc. MT8985 AC Electrical Characteristics- Microprocessor Bus Voltages are with respect to ground (VSS) unless otherwise stated. Data Sheet Characteristics 1 2 3 4 5 6 7 8 9 CS Setup from DS rising R/W Setup from DS rising Add setup from DS rising CS hold after DS falling R/W hold after DS falling Add hold after DS falling Data setup from DTA Low on Read Data hold on read Data setup on write (fast write) Sym. tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tSWD tDHW tAKD Min. 0 30 5 0 5 5 10 10 20 Typ. Max. Units ns ns ns ns ns ns ns Test Conditions CL=150 pF RL=1 K*, CL=150 pF 50 90 ns ns 10 Valid Data Delay on write (slow write) 11 Data hold on write 12 Acknowledgement Delay: Reading Data Memory Reading/Writing Conn. Memory Writing to Control Register Reading Control Register 13 Acknowledgement Hold Time 122 8 560 300/370 47 70 1220 730/800 95 155 110 ns ns ns ns ns ns ns CL=150 pF tAKH 10 60 RL=1 K*, CL=150 pF Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 21 Zarlink Semiconductor Inc. MT8985 2.0V DS 0.8V 2.0V 0.8V tRWS R/W 2.0V 0.8V tADS A0-A6 2.0V 0.8V D0-D7 2.0V READ 0.8V tSWD D0-D7 2.0V WRITE 0.8V tDDR tAKD DTA 2.0V 0.8V tADH tCSS tCSH tRWH Data Sheet CS VALID DATA tDSW VALID DATA tDHW tAKH tDHR Figure 17 - Motorola Non-Multiplexed Bus Timing 22 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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